Power gate with metal on both sides

ABSTRACT

An apparatus including a circuit structure including a device stratum including a plurality of transistor devices each including a first side defined by a gate electrode and an opposite second side; and a gated supply grid disposed on the second side of the structure, wherein a drain of the at least one of the plurality of transistor devices is coupled to the gated supply grid. A method including providing a supply from a package substrate to power gate transistors in a device layer of a circuit structure, the transistors coupled to circuitry operable to receive a gated supply from the power gate transistors; and distributing the gated supply from the power gate transistors to the circuitry using a grid on an underside of the device layer.

CROSS-REFERENCE TO RELATED APPLICATION

This patent application is a divisional of U.S. patent application Ser.No. 15/746,799, filed Jan. 22, 2018, which is a U.S. National PhaseApplication under 35 U.S.C. § 371 of International Application No.PCT/US2015/052375, filed Sep. 25, 2015, entitled “POWER GATE WITH METALON BOTH SIDES,” which designates the United States of America, theentire disclosure of which are hereby incorporated by reference in theirentirety and for all purposes.

TECHNICAL FIELD

Semiconductor devices including devices including electrical connectionsfrom a backside of the device.

BACKGROUND

For the past several decades, the scaling of features in integratedcircuits has been a driving force behind an ever-growing semiconductorindustry. Scaling to smaller and smaller features enables increaseddensities of functional units on the limited real estate ofsemiconductor chips. For example, shrinking transistor size allows forthe incorporation of an increased number of memory devices on a chip,lending to the fabrication of products with increased capacity. Thedrive for ever-more capacity, however, is not without issue. Thenecessity to optimize the performance of each device becomesincreasingly significant.

Future circuit devices, such as central processing unit devices, willdesire both high performance devices and low capacitance, low powerdevices integrated in a single die or chip.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a general diagram of a power gating scheme for supplyingpower to core logic in a processor.

FIG. 2 shows a cross-sectional schematic side view of an embodiment ofan assembly including an integrated circuit chip or die connected to apackage substrate.

FIG. 3 shows a top side perspective view of a portion of a semiconductoror semiconductor-on-insulator (SOI) substrate that is, for example, aportion of an integrated circuit die or chip on a wafer and illustratesa three-dimensional transistor device formed thereon with aninterconnect to the gate electrode of the transistor.

FIGS. 4A-4C show cross-sectional side views through the structure ofFIG. 2.

FIGS. 5A-5C show the structures of FIGS. 4A-4C following the invertingor flipping of the structure and connection of the structure to acarrier.

FIGS. 6A-6C show the structure of FIGS. 5A-5C following the removal orthinning of the device substrate to expose a second side or backside ofa fin of the transistor and following a recessing of the fin.

FIGS. 7A-7C shows the structure of FIGS. 6A-6C following the depositionand patterning of a dielectric material on a backside of a fin.

FIGS. 8A-8C show the structure of FIGS. 7A-7C following an epitaxialgrowth of a material for a backside junction formation.

FIGS. 9A-9C show the structure of FIGS. 8A-8C following the filling ofthe via openings in the dielectric material with a conductive contactmaterial such as a tungsten.

FIGS. 10A-10C shows the structure of FIGS. 9A-9C and show theinterconnect connected to a contact to a source and the interconnectconnected to a contact to a source as part of, for example, a firstbackside interconnect or metal layer.

FIGS. 11A-11C show the structure of FIGS. 10A-10C following the formingof multiple interconnect layers on the structure and contact points forconnection of the structure to an external substrate.

FIG. 12 shows the structure of FIG. 2 through line 12-12′ andillustrates the arrangement of interconnects of metal lines underneathor on a second side of the device strata.

FIG. 13 shows a cross-section representatively through line 13-13′ ofFIG. 2 to indicate a representative routing for a control line input tothe gate electrodes of the power transistors.

FIG. 14 is an interposer implementing one or more embodiments.

FIG. 15 illustrates an embodiment of a computing device.

DETAILED DESCRIPTION

The embodiments described herein are directed to semiconductor devicesincluding non-planar semiconductor devices (e.g., three-dimensionaldevices) having interconnects or wiring on an underside or backside ofthe devices, particularly interconnects providing gated power to corelogic circuitry. The distribution of gated power is described with powerwires (V_(DD), V_(DD)-gated, and V_(SS)) under a device layer of acircuit structure is described. In one embodiment, an apparatus isdisclosed including a circuit structure including a device stratumincluding a plurality of transistor devices such as, but not limited to,three dimensional or non-planar transistor devices each including afirst side or device side defined by a gate electrode on an oppositesecond side. A gated supply grid is disposed on a second side (backsideor underside) of the stratum, wherein a drain of the at least oneplurality of transistor devices is coupled to the gated supply grid. Asupply grid may also be disposed on the second side of the structure anda source of the at least one plurality of transistor devices may becoupled to the supply grid. By controlling the at least one transistordevice through, for example, controlling the gate electrode, a powersupply (V_(DD)) may be controlled. In another embodiment, a method isdescribed. The method includes providing a supply from a packagesubstrate to power gate transistors in a device layer of a circuitstructure, where the transistors are connected to circuitry operable toreceive a gated supply from the power gate transistors. The method alsoincludes distributing the gated supply from the power transistors to thecircuitry using a grid on an underside of the device stratum. Furtherdisclosed is a system including a package substrate including a supplyconnection and a die. The die includes core logic circuitry to receiveone or more gated supplies and a plurality of transistors defining adevice stratum and coupled between the supply connection and the corelogic circuitry to control or provide the one or more gated supplies tothe core logic circuitry. The gated supplies from the power gatetransistors to the circuitry is routed on an underside of the devicestratum.

FIG. 1 shows a general diagram of a power gating scheme for supplyingpower to core logic in a processor. Representatively, a P-type gatelabeled “PG” is connected in series between ungated power supply(V_(DD)) and core logic 102. The P-type gate labeled PG is representedwith a single P-type transistor. It is appreciated that numerous (e.g.,hundreds of thousands or millions) of PG transistors may be utilizedover a region of an integrated circuit structure. In addition, whilecore logic 102 is shown, any functional group(s) of circuitry in anysuitable integrated circuit may be gated as described herein. Controltransistors M1, M2 are connected as shown and controlled with Inactive #signal (M1) and an Active signal (M2). When Inactive # is asserted(Low), Active will be de-asserted (Low), which causes an increase supply(V_(DD) High) to be applied to PG to turn it off, which decouples (orstrongly reduces) the V_(DD) supply from core logic 102. When thecircuit is in Active mode, the Active signal is asserted (High) andInactive # is de-asserted (High) to turn on PG and couple the V_(DD)supply to core logic 102. The use of power gates, as described herein,can allow for significant reduction of leakage powering processor chips.Power gating involves intercepting the voltage supply network fromfunctional circuitry and may be used either on positive or negativesupply branches. For simplicity sake, the description that followsprimarily focuses on the use of positive power supply gating, butembodiments may also incorporated negative supply gating as well.

FIG. 2 shows a cross-sectional schematic side view of one embodiment ofan assembly including an integrated circuit chip or die connected to apackage substrate. Assembly 200 includes die 210 that includes devicelayer or stratum 215 including a number of devices (e.g., transistordevices). Device stratum 215 includes first side 2150A representing afirst side of the stratum and second side or backside 2150B oppositefirst side 2150A. The transistor devices include one or more powertransistors (also referenced herein as power gates) and logic circuitry.Connected to device stratum 215 of die 210 on a first side areinterconnects 220 that, in one embodiment, include, but are not limitedto, a number of conductive metal lines connected to devices of devicestratum 215 from first side 2150A. Included among the interconnects arecontrol circuitry interconnects. Disposed above signal wiring 220, asviewed, is carrier substrate 240. In one embodiment, as will bedescribed below, carrier substrate 240 is bonded to signal wiring 220 ina process of forming die 210 with metallization on both sides of thelogic circuitry. Connected to devices of die 210 through second side2100B of the die, in this embodiment, are power interconnects (V_(DD),V_(DD)-gated and V_(SS)). Interconnects 230 on second side or backside2100B include one or more rows of metallization. Ones of suchmetallization are connected to contact points (e.g., C4 bumps) 250 thatare operable to connect die 210 to package 290. FIG. 2 also shows V_(DD)and V_(SS) connections to die 210 through package substrate 290.

FIGS. 3-11C describe a method or process of forming a die including apower gate implemented in a single device stratum utilizing non-planarmulti-gate semiconductor devices including electrical connections on anon-device side or backside of the stratum (underneath the devices).Such electrical connections include power wires V_(DD), V_(DD)-gated,and V_(SS). Signal wiring (control wiring), in this embodiment, isdisposed above the devices. In one embodiment, the devices used in thedevice strata are three-dimensional metal oxide semi-conductor fieldeffect transistors (MOSFETs).

FIG. 3 shows a top side perspective view of a portion of a semiconductoror semiconductor-on-insulator (SOI) substrate that is, for example, aportion of an integrated circuit die or chip on a wafer. Specifically,FIG. 3 shows structure 300 including substrate 310 of silicon or SOI.Overlaying substrate 310 is optional buffer layer 320. In oneembodiment, a buffer layer is a silicon germanium buffer introduced, inone embodiment, on substrate 310 by a growth technique.Representatively, buffer layer 320, if present, has a representativethickness on the order of a few hundred nanometers (nm).

Disposed on a surface of substrate 310 and optional buffer layer 320 inthe embodiment illustrated in FIG. 3 (an upper surface as viewed), is aportion of a transistor device such as an N-type transistor device or aP-type transistor device. Common to an N-type or P-type transistordevice, in this embodiment, is body or fin 330 disposed on a surface ofbuffer layer 320. In one embodiment, fin 330 is formed of asemiconductor material such as silicon, silicon germanium or a groupIII-V or group IV-V semiconductor material. In one embodiment, amaterial of fin 330 is formed according to conventional processingtechniques for forming a three-dimensional integrated circuit device.Representatively, a semiconductor material is epitaxially grown on thesubstrate and then formed into fin 330 (e.g., by a masking and etchprocess).

In one embodiment, fin 330 has a length dimension, L, greater than aheight dimension, H. A representative length range is on the order of 10nanometers (nm) to 1 millimeter (mm), and a representative height rangeis on the order of 5 nm to 200 nm. Fin 330 also has a width, W,representatively on the order of 4-10 nm. As illustrated, fin 330 is athree-dimensional body extending from or on a surface of substrate 310(or optionally from or on buffer layer 320). The three-dimensional bodyas illustrated in FIG. 3 is a rectangular body with opposing sides(first and second sides) projecting from a surface of buffer layer 320as viewed. It is appreciated that in processing of such bodies, a truerectangular form may not be achievable with available tooling, and othershapes may result. Representative shapes include, but are not limitedto, a trapezoidal shape (e.g., base wider than top) and an arch shape.

Disposed on fin 330 in the embodiment of a structure of FIG. 3 is a gatestack. In one embodiment, a gate stack includes a gate dielectric layerof, for example, silicon dioxide or a dielectric material having adielectric constant greater than silicon dioxide (a high k dielectricmaterial). Disposed on the gate dielectric layer, in one embodiment, isgate 325 of, for example, a metal. The gate stack may include spacers350 of dielectric material on opposite sides thereof. A representativematerial for spacers 350 is a low k material such as silicon nitride(SiN) or silicon carbon nitrogen (SiCN). FIG. 3 shows spacers 350adjacent the sidewalls of the gate stack and on the fin 330. Formed onor in fin 330 on opposite sides of the gate stack are junction regions(source 340A and drain 340B).

In one embodiment, to form the three-dimensional transistor structure, agate dielectric material is formed on fin 330 such as by way of ablanket deposition followed by a blanket deposition of a sacrificial ordummy gate material. A mask material is introduced over the structureand patterned to protect the gate stack material (gate stack withsacrificial or dummy gate material) over a designated channel region. Anetch process is then used to remove the gate stack material in undesiredareas and pattern the gate stack over a designated channel region.Spacers 350 are then formed. One technique to form spacers 350 is todeposit a film on the structure, protect the film in a desired area andthen etch to pattern the film into desired spacer dimensions.

Following the formation of a gate stack including a sacrificial or dummygate material on fin 330 and spacers 350, junction regions (source anddrain) are formed on or in fin 330. The source and drain are formed inor on fin 330 on opposite sides of the gate stack (sacrificial gateelectrode on gate dielectric). In the embodiment shown in FIG. 3, source340A and drain 340B are formed by epitaxially growing source and drainmaterial as a cladding on a portion of fin 330. Representative materialfor source 340A and drain 340B includes, but is not limited to, silicon,silicon germanium, or a group III-V or group IV-V compound semiconductormaterial. Source 340A and drain 340B may alternatively be formed byremoving portions of the fin material and epitaxially growing source anddrain material in designated junction regions where fin material wasremoved.

Following the formation of source 340A and drain 340B, in oneembodiment, the sacrificial or dummy gate is removed and replaced with agate electrode material. In one embodiment, prior to removal of thesacrificial or dummy gate stack, a dielectric material is deposited onthe structure. In one embodiment, dielectric material is silicon dioxideor a low k dielectric material deposited as a blanket and then polishedto expose sacrificial or dummy gate 325. The sacrificial or dummy gateand gate dielectric are then removed by, for example, an etch process.

Following a removal of the sacrificial or dummy gate and gatedielectric, a gate stack is formed in a gate electrode region. A gatestack is introduced, e.g., deposited, on the structure including a gatedielectric and gate electrode. In an embodiment, gate electrode 325 ofthe gate electrode stack is composed of a metal gate and a gatedielectric layer is composed of a material having a dielectric constantgreater than a dielectric constant of silicon dioxide (a high-Kmaterial). For example, in one embodiment, gate dielectric layer 327(see FIGS. 4A-4C) is composed of a material such as, but not limited to,hafnium oxide, hafnium oxy-nitride, hafnium silicate, lanthanum oxide,zirconium oxide, zirconium silicate, tantalum oxide, barium strontiumtitanate, barium titanate, strontium titanate, yttrium oxide, aluminumoxide, lead scandium tantalum oxide, lead zinc niobate, or a combinationthereof. In one embodiment, gate electrode 325 is composed of a metallayer such as, but not limited to, metal nitrides, metal carbides, metalsilicides, metal aluminides, hafnium, zirconium, titanium, tantalum,aluminum, ruthenium, palladium, platinum, cobalt, nickel or conductivemetal oxides. Following the formation of the gate stack, additionaldielectric material dielectric material of silicon dioxide or a low kdielectric material is deposited on the three-dimensional transistordevice (e.g., on ILD0) to encapsulate or embed the device structure indielectric material. FIG. 3 shows dielectric material 355A encapsulatingthe three-dimensional transistor device (e.g., as an ILD0).

FIG. 3 shows the structure following the forming of interconnects to thethree-dimensional transistor device structure. In this embodiment, anelectrical connection is made as a first interconnect layer or metallayer to gate electrode 325. Representatively, to form an electricalcontact to gate electrode 375, an opening is initially formed to thegate electrode by, for example, a masking process with an opening in amask to gate electrode 325. Dielectric material 355A is etched to exposethe gate electrode and then the masking material removed. Next, acontact material of, for example, tungsten is introduced in the openingand the opening is filled to form contact 375 to gate electrode 325. Asurface of dielectric material 355A (a top surface as viewed) may thenbe seeded with a conductive seed material and then patterned withmasking material to define an opening for an interconnect path with theopening exposing contact 375. A conductive material such as copper isthen introduced by way of an electroplating process to form interconnect370 connected to contact 375 of gate electrode 325. The masking materialand unwanted seed material can then be removed. Following the formationof interconnects as an initial metal layer, dielectric material 355B offor example, silicon dioxide or a low k dielectric material may bedeposited as an ILD1 layer on and around the interconnects. Additionalinterconnect layers may then be formed according to conventionalprocesses. FIG. 2 shows signal wiring 220 of die 210 comprised ofseveral layers of interconnect. Interconnect 370 in FIG. 3 isrepresentative of one, for example, a first of such layers nearest thedevice layer.

FIGS. 4A-4C show cross-sectional side views through the structure ofFIG. 2. Specifically, FIG. 4A shows a cross-section through line A-A′through fin 330; FIG. 4B shows a cross-section through line B-B′ throughsource 340A; and FIG. 4C shows a cross-sectional side view through lineC-C′ through gate electrode 325.

FIGS. 5A-5C show the structures of FIGS. 4A-4C following the invertingor flipping of the structure and connection of the structure to acarrier. FIGS. 5A-5C represent cross-sections through fin 330, drain340B, and gate electrode 325, respectively, as described above withrespect to FIGS. 4A-4C. Referring to FIGS. 5A-5C, in this embodiment,structure 300 is flipped and connected to carrier 380. Carrier 380 is,for example, a semiconductor wafer. Structure 300 may be connected tocarrier 380 through an adhesive or other bonding technique.

FIGS. 6A-6C show the structure of FIGS. 5A-5C following the removal orthinning of substrate 310 to expose a second side or backside of fin330. In one embodiment, substrate 310 may be removed by a thinningprocess, such as a mechanical grinding or etch process. FIGS. 6A-6C showfin 330 exposed from a second side or backside of the structure.Following exposure of fin 330, the fin may optionally be recessed. FIGS.6A-6C show the structure following a recessing of fin 330. In oneembodiment, to recess fin 330, an etch process may be utilized with anetchant selective toward a removal of fin material relative todielectric material 355A. Alternatively, a masking material may bepatterned on a surface of dielectric material 355A (an exposed backsidesurface) with an opening that exposes fin 330. A material of fin 330 maybe removed to recess fin 330 by, for example, an etch process, and thenthe masking material removed.

FIGS. 7A-7C shows the structure of FIGS. 6A-6C following the depositionand patterning of a dielectric material on a backside of fin 330. FIGS.7A-7C show dielectric material 381 of, for example, a silicon dioxide ora low K dielectric material deposited by for example, a blanketdeposition process. Once deposited, dielectric material 381 may bepatterned by, for example, forming a masking material on a surface ofdielectric material 380 with openings or vias opposite, for example,source and drain regions on an opposite side of fin 330. FIG. 7A showsopening 382A through dielectric material 381 oriented on a backside offin 330 corresponding to a source region of the fin (source 340A) andopening 382B through dielectric material 381 oriented to a drain regionof the fin (drain 340B). FIG. 7B shows that, in this embodiment, theopenings (e.g., opening 382A) have dimensions for a diameter that isgreater than a width dimension of fin 330. In this manner, a backside offin 330 as well as side walls of fin 330 are exposed. FIG. 7B also showsthat the etch proceeds through the structure to expose a backside ofsource 340A.

FIGS. 8A-8C show the structure of FIGS. 7A-7C following an epitaxialgrowth of a material for a backside junction formation. FIG. 8A showsepitaxially grown material 385A in opening 382A in a region aligned witha backside of source 340A and epitaxially grown material 385B in opening382B on fin 330 aligned with a backside of drain 340B. FIG. 8B showsmaterial 385A epitaxially grown on the side walls of fin 330 andconnecting with source 340A previously formed on a first side or deviceside of the structure. A suitable material is silicon germanium or agroup III-V or group IV-V semiconductor material.

FIGS. 9A-9C show the structure of FIGS. 8A-8C following the filling ofthe via openings in dielectric material 380 with a conductive contactmaterial such as a tungsten. FIG. 9A shows contact 386A to epitaxialmaterial 385B associated with source 340A and contact metal 386B toepitaxial material 385B associated with drain 340B. FIG. 9B showscontact metal 386B to epitaxial material 385B. FIGS. 9A and 9B also showthe connection to source 340A (via contact material) from a backside orsecond side of the structure an underside of the device stratum.Interconnects may now be formed to contacts 386A and 386B by, forexample, the technique described above with respect to device sideinterconnects (see FIGS. 3 and 4A-4C and the accompanying text).

The above description of forming backside junction (source and drain)contacts is one embodiment. It is appreciated that there are othermethods rather than an epitaxial growth of a material on the fin. Otherembodiments include, but are not limited to, modifying regions of thefin from the backside by, for example, driving in dopants. In anotherembodiment, the sidewalls of fin 330 may be exposed in source an drainregions and a contact material such as tungsten may be introduced onsuch sidewalls. Where contact material is also formed on a device sideof the source and drain (e.g., forming such contacts at the time offorming contact 375 to gate electrode 325), the contact may be extendedin a backside processing operation to forma wrap-around contact to thesource and drain, respectively.

FIGS. 10A-10C shows the structure of FIGS. 9A-9C and show interconnect390A connected to contact 396A to source 340A and interconnect 390Bconnected to contact 386B to source 340B as part of, for example, afirst backside interconnect or metal layer. FIGS. 10A-10C also show thestructure following the deposition of dielectric material 355C ofsilicon dioxide or a low k dielectric material on the interconnect ormetal layer.

In one embodiment, a first backside interconnect or metal layerincluding interconnect 390A and interconnect 390B is part of or isconnected to a power grid underneath or on a backside of the devicestratum. Representatively, where the transistor described with referenceto FIGS. 3-10C is a power gate transistor (PG in FIG. 1), source 340A isconnected to V_(DD) and drain 340B is connected to V_(DD)-gated.

FIGS. 11A-11C show the structure of FIGS. 10A-10C following the formingof multiple interconnect layers on the structure and contact points forconnection of the structure to an external substrate. The interconnectsof such layers may be formed by an electroplating process. In oneembodiment, such interconnects of a conductive material such as coppermay be doped with a dopant to improve electromigration. FIG. 11A showsinterconnect 390A that is, in one embodiment, a V_(DD) line to source340A and interconnect line 390B that is a V_(DD)-gated line connected todrain 340B. Interconnect 390A is connected to interconnect 394 that is,for example, a second backside level V_(DD) line through contact 392A.Similarly, interconnect line 390B is connected to a second backsideinterconnect layer that is a V_(DD)-gated line that is, for example,connected to one or more other transistor devices (e.g., connected to asource of one or more transistor through an underside or backsideconnection that make up core logic. V_(DD) interconnect line 394 isconnected to a third level backside interconnect 395 that is connectedto contact point 397 operable to bring power (V_(DD)) to the structure.As illustrated, each of the interconnect levels is separated from anadjoining level by dielectric material (dielectric material 355C,dielectric material 355D, and dielectric material 355E). Contact points397 are, for example, C4 bumps operable to connect the structure to asubstrate such as a package substrate.

FIG. 12 shows the structure of FIG. 2 through line 12-12′ andillustrates the arrangement of interconnects of metal lines underneathor on a second side of the device stratum. Reference numbers used inFIG. 12 are similar to those of FIGS. 11A-11C for purposes ofcoordinating FIG. 12 with prior discussion. In the illustration shown inFIG. 12, the dark dashed line is a region reserved for the powertransistor. It is appreciated that the power transistor region could beany number of gate pitches wide. The power transistor is shown as anumber of rows of V_(DD) (e.g., interconnect line 395 and V_(DD)-gatedHigh) (e.g., interconnect line 396). Disposed on the V_(DD) andV_(DD)-gated High lines in the power gate region are anotherinterconnect layer for connection to the device stratum from anunderside. Overlying V_(DD) and V_(DD)-gated lines and the power gateregion are first level backside interconnects such as interconnect 390Afor connection to source regions of transistor devices and interconnects390B for connection to drain regions of interconnect devices. FIG. 12shows contacts between the source interconnects (interconnect 390A) anda V_(DD) line interconnect 395 (through contact 392A). Similarly, FIG.12 shows contacts between drain interconnects (interconnect 390B) and aV_(DD)-gated line (contact 392B).

FIG. 13 shows a cross-section representatively through line 13-13′ ofFIG. 2 to indicate a representative routing for a control line input tothe gate electrodes of the power transistors. Reference is again made toFIGS. 11A-11C for reference number coordination. In FIG. 13, the devicelayer is not shown to illustrate the metallization (e.g.,three-dimensional transistors not shown). FIG. 13 shows a first levelinterconnection line on a first side of a device stratum (interconnectline 370) ones of those interconnect lines (e.g., interconnect line 370)are connected to gate electrodes of the field effect transistors in thepower gate region. FIG. 13 shows interconnect 370 and contact 375 thatextends between the interconnect and a gate electrode of a transistordevice (see FIGS. 10A-10C). Overlying the first interconnect layerincluding interconnect layer 370 is a second interconnect layerincluding interconnect line 410. FIG. 13 shows the connection ofinterconnect line 410 to the underlying interconnect layer andillustrates contact 425 to underlying interconnect 370. Interconnectline 410 is a control line input to a gate of a field effect transistorin the power gate region of the structure (see PG in FIG. 1). Theconnection can be located vertically up or down (as viewed) as long asit lands on the gate electrode connection and meets other design rules.

In the above embodiments, interconnects or metal layers are disposed onboth sides of a device stratum. As described, the V_(DD) andV_(DD)-gated are gridded underneath the field effect transistor devicealong with V_(SS) for connection to ground. As described, only thecontrol line to a gate of a field effect transistor or power fieldeffect transistor is disposed on a device side or first side of thedevice. Such control line can be fine pitch like other control lines ona device side or first side of the structure. The routing of the powerlines underneath or on a second side of a device stratum preserves theroutability of metal layers on a device side or first side. Providingpower lines on an under side or second side of a device stratum alsoallows doping of the metal materials (typically copper) that form theinterconnect or metal lines. Such interconnects or metal lines may bedoped to achieve high electromigration prevention while keeping theadditional resistance of such metal doping out of signal wires on adevice side or first side of the structure. In addition, by not bringingV_(DD) and V_(DD)-gated through the device layer silicon area for logictransistors is preserved. Still further, by positioning the power linesunderneath or on a second side of a device stratum that also includesthe contacts for the structure to a substrate such as a packetsubstrate, reduction in via resistance and metal resistance from suchcontact points to delivery to the power gate for V_(DD) is reduced.

FIG. 14 illustrates interposer 500 that includes one or moreembodiments. Interposer 500 is an intervening substrate used to bridge afirst substrate 502 to second substrate 504. With reference to FIG. 2above, interposer 500 may be, for example, placed between chip or die210 and package 290. In another embodiment, first substrate 502 may be,for instance, an integrated circuit die. Second substrate 504 may be,for instance, a memory module, a computer motherboard, or anotherintegrated circuit die. Generally, the purpose of interposer 500 is tospread a connection to a wider pitch or to reroute a connection to adifferent connection. For example, an interposer 500 may couple anintegrated circuit die to a ball grid array (BGA) 506 that cansubsequently be coupled to the second substrate 504. In someembodiments, the first and second substrates 502/504 are attached toopposing sides of interposer 500. In other embodiments, the first andsecond substrates 502/504 are attached to the same side of interposer500. In further embodiments, three or more substrates are interconnectedby way of interposer 500.

The interposer 500 may be formed of an epoxy resin, afiberglass-reinforced epoxy resin, a ceramic material, or a polymermaterial such as polyimide. In further implementations, the interposermay be formed of alternate rigid or flexible materials that may includethe same materials described above for use in a semiconductor substrate,such as silicon, germanium, and other group III-V and group IVmaterials.

The interposer may include metal interconnects 508 and vias 510,including but not limited to through-silicon vias (TSVs) 512. Theinterposer 500 may further include embedded devices 514, including bothpassive and active devices. Such devices include, but are not limitedto, capacitors, decoupling capacitors, resistors, inductors, fuses,diodes, transformers, sensors, and electrostatic discharge (ESD)devices. More complex devices such as radio-frequency (RF) devices,power amplifiers, power management devices, antennas, arrays, sensors,and MEMS devices may also be formed on interposer 500.

In accordance with embodiments, apparatuses or processes disclosedherein may be used in the fabrication of interposer 500.

FIG. 15 illustrates a computing device 600 in accordance with oneembodiment. The computing device 600 may include a number of components.In one embodiment, these components are attached to one or moremotherboards. In an alternate embodiment, these components arefabricated onto a single system-on-a-chip (SoC) die rather than amotherboard. The components in the computing device 600 include, but arenot limited to, an integrated circuit die 602 and at least onecommunication chip 608. In some implementations the communication chip608 is fabricated as part of the integrated circuit die 602. Theintegrated circuit die 602 may include a CPU 604 as well as on-diememory 606, often used as cache memory, that can be provided bytechnologies such as embedded DRAM (eDRAM) or spin-transfer torquememory (STTM or STTM-RAM).

Computing device 600 may include other components that may or may not bephysically and electrically coupled to the motherboard or fabricatedwithin an SoC die. These other components include, but are not limitedto, volatile memory 610 (e.g., DRAM), non-volatile memory 612 (e.g., ROMor flash memory), a graphics processing unit 614 (GPU), a digital signalprocessor 616, a crypto processor 642 (a specialized processor thatexecutes cryptographic algorithms within hardware), a chipset 620, anantenna 622, a display or a touchscreen display 624, a touchscreencontroller 626, a battery 628 or other power source, a power amplifier(not shown), a global positioning system (GPS) device 644, a compass630, a motion coprocessor or sensors 632 (that may include anaccelerometer, a gyroscope, and a compass), a speaker 634, a camera 636,user input devices 638 (such as a keyboard, mouse, stylus, andtouchpad), and a mass storage device 640 (such as hard disk drive,compact disk (CD), digital versatile disk (DVD), and so forth).

The communications chip 608 enables wireless communications for thetransfer of data to and from the computing device 600. The term“wireless” and its derivatives may be used to describe circuits,devices, systems, methods, techniques, communications channels, etc.,that may communicate data through the use of modulated electromagneticradiation through a non-solid medium. The term does not imply that theassociated devices do not contain any wires, although in someembodiments they might not. The communication chip 608 may implement anyof a number of wireless standards or protocols, including but notlimited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE,GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well asany other wireless protocols that are designated as 3G, 4G, 5G, andbeyond. The computing device 600 may include a plurality ofcommunication chips 608. For instance, a first communication chip 608may be dedicated to shorter range wireless communications such as Wi-Fiand Bluetooth and a second communication chip 608 may be dedicated tolonger range wireless communications such as GPS, EDGE, GPRS, CDMA,WiMAX, LTE, Ev-DO, and others.

The processor 604 of the computing device 600 includes one or moredevices, such as transistors or metal interconnects, that are formed inaccordance with embodiments including backside contacts to device andbackside metallization. The term “processor” may refer to any device orportion of a device that processes electronic data from registers and/ormemory to transform that electronic data into other electronic data thatmay be stored in registers and/or memory.

The communication chip 608 may also include one or more devices, such astransistors or metal interconnects, that are formed in accordance withembodiments including backside contacts to device and backsidemetallization.

In further embodiments, another component housed within the computingdevice 600 may contain one or more devices, such as transistors or metalinterconnects, that are formed in accordance with implementationsincluding backside contacts to device and backside metallization.

In various embodiments, the computing device 600 may be a laptopcomputer, a netbook computer, a notebook computer, an ultrabookcomputer, a smartphone, a tablet, a personal digital assistant (PDA), anultra mobile PC, a mobile phone, a desktop computer, a server, aprinter, a scanner, a monitor, a set-top box, an entertainment controlunit, a digital camera, a portable music player, or a digital videorecorder. In further implementations, the computing device 600 may beany other electronic device that processes data.

EXAMPLES

Example 1 is an apparatus including a circuit structure including adevice stratum including a plurality of transistor devices eachincluding a first side defined by a gate electrode and an oppositesecond side; and a gated supply grid disposed on the second side of thestructure, wherein a drain of the at least one of the plurality oftransistor devices is coupled to the gated supply grid.

In Example 2, the apparatus of Example 1 further includes a supply griddisposed on the second side of the structure, wherein a source of atleast one of the plurality of transistor devices is coupled to thesupply grid.

In Example 3, the apparatus of any of Example 1 or 2 further includes acontrol line disposed on a first side of the structure, wherein the gateelectrode of the at least one of the plurality of transistor devices iscoupled to the control line.

In Example 4, the gate electrode of the at least one of the plurality oftransistor devices of the apparatus of Example 3 is coupled to thecontrol line through a gate contact projecting between the device andthe control line and the drain of the device is coupled to the gatedsupply grid through a junction contact projecting between the device andthe gated supply grid.

In Example 5, the drain of the at least one of the plurality oftransistor devices of the apparatus of any of Examples 1˜4 is coupled tothe gated supply grid through a contact extending between the gatedsupply grid and the second side of the device.

In Example 6, the apparatus of any of Examples 1-5 further includes acontact point operable to couple the circuit structure to an externalpower source, the contact point disposed coupled to the supply grid onthe second side of the structure.

In Example 7, the gated supply grid of the apparatus of any of Examples1-6 includes a power grid, the apparatus further including a ground griddisposed on the second side of the structure.

In Example 8, the at least one of the transistor devices of theapparatus of any of Examples 1-7 includes a non-planar transistor deviceincluding a fin and the gate electrode is disposed on the channel regionof the fin.

Example 9 is a method including providing a supply from a packagesubstrate to power gate transistors in a device layer of a circuitstructure, the transistors coupled to circuitry operable to receive agated supply from the power gate transistors; and distributing the gatedsupply from the power gate transistors to the circuitry using a grid onan underside of the device layer.

In Example 10, providing a supply to power gate transistors in themethod of Example 9 includes coupling to the transistors from theunderside of the device layer.

In Example 11, providing a supply to power gate transistors in themethod of Example 9 or 10 includes distributing the supply from thepackage substrate using a grid on the underside of the device layer.

In Example 12, distributing the gated supply from the power gatetransistors in the method of any of Examples 9-11 includes coupling thetransistors to the grid from the underside of the transistors.

In Example 13, the method of any of Examples 9-12 further includescontrolling the gated supply from a control line coupled to thetransistors on a side opposite the underside of the transistors.

In Example 14, the method of any of Examples 9-13 further includesdistributing a ground grid on the underside of the device layer, theground grid coupled to the circuitry.

Example 15 is a system including a package substrate including a supplyconnection, and a die including (i) core logic circuitry to receive oneor more gated supplies, and (ii) a plurality of transistors defining adevice layer and coupled between the supply connection and the corelogic circuitry to controllably provide the one or more gated suppliesto the core logic circuitry, wherein the gated supplies to the circuitryis routed on an underside of the device layer.

In Example 16, the one or more gated supplies in the system of Example15 are coupled to the plurality of transistors from the underside of thedevice layer.

In Example 17, a supply connection to the power gate transistors in thesystem of any of Examples 15-16 includes a grid on the underside of thedevice layer.

In Example 18, distributing the gated supply from the power gatetransistors in the system of any of Examples 15-17 includes coupling thetransistors to the grid from the underside of the transistors.

In Example 19, the system of any of Examples 15-18 further includescontrolling the gated supply from a control line coupled to theplurality of transistors on a side opposite the underside of thetransistors.

In Example 20, at least one of the plurality of transistors in thesystem of any of Examples 15-19 includes a non-planar transistor.

The above description of illustrated implementations, including what isdescribed in the Abstract, is not intended to be exhaustive or to limitthe invention to the precise forms disclosed. While specificimplementations of, and examples for, the invention are described hereinfor illustrative purposes, various equivalent modifications are possiblewithin the scope, as those skilled in the relevant art will recognize.

These modifications may be made in light of the above detaileddescription. The terms used in the following claims should not beconstrued to limit the invention to the specific implementationsdisclosed in the specification and the claims. Rather, the scope of theinvention is to be determined entirely by the following claims, whichare to be construed in accordance with established doctrines of claiminterpretation.

1. A method comprising: providing a supply from a package substrate topower gate transistors in a device layer of a circuit structure, thetransistors coupled to circuitry operable to receive a gated supply fromthe power gate transistors; and distributing the gated supply from thepower gate transistors to the circuitry using a grid on an underside ofthe device layer.
 2. The method of claim 1, wherein providing a supplyto power gate transistors comprises coupling to the transistors from theunderside of the device layer.
 3. The method of claim 1, whereinproviding a supply to power gate transistors comprises distributing thesupply from the package substrate using a grid on the underside of thedevice layer.
 4. The method of claim 1, wherein distributing the gatedsupply from the power gate transistors comprises coupling thetransistors to the grid from the underside of the transistors.
 5. Themethod of claim 1, further comprising controlling the gated supply froma control line coupled to the transistors on a side opposite theunderside of the transistors.
 6. The method of claim 1, furthercomprising distributing a ground grid on the underside of the devicelayer, the ground grid coupled to the circuitry.
 7. A method offabricating an apparatus, the method comprising: forming a circuitstructure comprising a device stratum comprising a plurality oftransistor devices, the device stratum having a first side and a secondside opposite the first side, each of the plurality of transistorscomprising a gate electrode on the first side of the device stratum; andforming a gated supply grid on the second side of the device stratum,wherein a drain of the at least one of the plurality of transistordevices is coupled to the gated supply grid, wherein the drain of the atleast one of the plurality of transistor devices is coupled to the gatedsupply grid through a contact, the contact on the second side of thedevice stratum and extending between the gated supply grid and thesecond side of the device stratum but not into the device stratum. 8.The method of claim 7, further comprising forming a supply grid on thesecond side of the device stratum, wherein a source of at least one ofthe plurality of transistor devices is coupled to the supply grid. 9.The method of claim 7, further comprising forming a control line on afirst side of the device stratum, wherein the gate electrode of the atleast one of the plurality of transistor devices is coupled to thecontrol line.
 10. The method of claim 10, wherein the gate electrode ofthe at least one of the plurality of transistor devices is coupled tothe control line through a gate contact projecting between the deviceand the control line and the drain of the device is coupled to the gatedsupply grid through a junction contact projecting between the device andthe gated supply grid.
 11. The method of claim 8, further comprisingforming a contact point operable to couple the circuit structure to anexternal power source, the contact point coupled to the supply grid onthe second side of the device stratum.
 12. The method of claim 7,wherein the gated supply grid comprises a power grid, the method furthercomprising forming a ground grid on the second side of the devicestratum.
 13. The method of claim 7, wherein the at least one of thetransistor devices comprises a non-planar transistor device comprising afin and the gate electrode is disposed on the channel region of the fin.14. A method of fabricating a system, the method comprising: providingcomprising a package substrate comprising a supply connection; andcoupling a die to the package substrate, the die comprising: (i) corelogic circuitry to receive one or more gated supplies, and (ii) aplurality of transistors defining a device layer and coupled between thesupply connection and the core logic circuitry to controllably providethe one or more gated supplies to the core logic circuitry, the devicelayer having a first side and an underside opposite the first side, eachof the plurality of transistors comprising a gate electrode on the firstside of the device layer, wherein the gated supplies to the circuitry isrouted on the underside of the device layer, wherein a drain of at leastone of the plurality of transistors is coupled to the gated suppliesthrough a contact, the contact on the underside of the device stratumand extending between the gated supplies and the underside of the devicelayer but not into the device layer.
 15. The method of claim 14, whereinthe one or more gated supplies are coupled to the plurality oftransistors from the underside of the device layer.
 16. The method ofclaim 14, wherein a supply connection to the power gate transistorscomprises a grid on the underside of the device layer.
 17. The method ofclaim 16, wherein distributing the gated supply from the power gatetransistors comprises coupling the transistors to the grid from theunderside of the device layer.
 18. The method of claim 14, furthercomprising controlling the gated supply from a control line coupled tothe plurality of transistors on the first side of the device layer. 19.The method of claim 14, wherein at least one of the plurality oftransistors comprises a non-planar transistor.